VHDLBench: Benchmarking and Fine-Tuning Large Language Models for VHDL-Based Chip Design
The rapid evolution of digital circuit complexity demands innovative approaches to hardware design automation. While Large Language Models (LLMs) have influenced software development, their application to Hardware Description Language (HDL) generation remains largely unexplored, particularly for VHDL. This paper presents a comprehensive study for AI-assisted digital circuit design, addressing gaps in current Electronic Design Automation workflows. The work introduces a VHDL dataset of 18,500+ syntax-verified examples from open-source repositories and converted Verilog designs. Five 7B-parameter LLMs were fine-tuned using parameter-efficient QLoRA technique, enabling deployment in resource...
| Authors | Patrik Drazic, Benaoumeur Senouci, Boualem Benatallah |
|---|---|
| Primary category | cs.AR |
| Published | 19 October 2026 |
| Last updated at source | 19 October 2026 |
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