Learn the Interface, Not the Implementation: Output Representation Dominates Training Regime in LLM-Based RTL Generation
Large-language-model register-transfer-level (RTL) generation has concentrated on how to train the model: fine-tuning, continued pre-training, and reinforcement learning from a verifier. We argue this is the second-order question. On a bounded, formally specifiable task of generating single-error-correcting, double-error-detecting (SECDED) ECC memory wrappers, we hold the task, data, and correctness oracle fixed and vary two axes independently: the training regime (seven settings) and the output representation (four levels, from fully expanded flat Verilog to an eight-field configuration expanded by a deterministic generator). Because a reference generator exists, correctness is decided b...
| Authors | Siddharth Patel, Vikram Singh, Siddharth Savyasachi Malu et al. |
|---|---|
| Primary category | cs.LG |
| Published | 19 October 2026 |
| Last updated at source | 19 October 2026 |
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