Formal-Verification-Guided Bayesian Optimization for Non-Intrusive Last-Mile Coverage Closure
Last-mile functional coverage closure for modern chip designs remains costly because a mature UVM environment exposes many controls while direct hits on the remaining bins are sparse. We present a non-intrusive workflow that closes pre-defined bins in an existing, human-authored functional coverage model; it does not synthesize verification objectives from the design specification. The workflow first uses abstract-syntax-tree (AST) parsing and cone-of-influence (COI) tracing to map each residual target to existing testbench knobs. Under a matched 20-simulation budget, Bayesian optimization (BO) is compared with continued constrained-random verification (CRV) and random search over the sam...
| Authors | Chengjia Liu, Priyadarsi Mishra, David Kebo Houngninou et al. |
|---|---|
| Primary category | cs.AR |
| Published | 12 October 2026 |
| Last updated at source | 12 October 2026 |
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