LATCH: LLM-Assisted Timing Closure Harness for Post-Route FPGA Optimisation
Post-route FPGA timing closure remains expert-dependent and computationally expensive. We present LATCH (LLM-Assisted Timing Closure Harness), a two-layer framework that separates large language model (LLM) orchestration from deterministic FPGA implementation and evaluation. Across sixteen designs and seven LLMs, a single-iteration study compares three agent control granularities - expert-written recipes, direct EDA operations and LLM-constructed procedures - to ask how much control an agent needs per attempt. Functional-pass rates are 98.2%, 71.4% and 17.9%, respectively; yet direct operations give slightly larger 3.4% median Fmax gains when passing, versus 3.2% for recipes. This exposes...
| Authors | Shu Gu, Matthew Youngman, Yuqin Zhao et al. |
|---|---|
| Primary category | cs.AI |
| Published | 12 October 2026 |
| Last updated at source | 12 October 2026 |
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