2d-fet-bench: from spatial reasoning to fet design on flakes
Field-effect transistor (FET) layouts on exfoliated two-dimensional flakes are typically drawn by hand for each flake, placing contacts and gates to match its position and outline in optical micrographs. To our knowledge, no executable benchmark tests whether language-model agents can perform this flake-specific construction reliably. We introduce 2D-FET-Bench V2, a benchmark of 128 layout tasks built from microscopy-derived flake contours, including hole-containing flakes and multi-flake tasks. Each task supplies a textual device specification and contour coordinates. An agent generates typed polygon and path operations rendered to GDSII. A deterministic verifier checks geometric and str...
| Authors | Dunzhi Zhou, Chengyu Zhu, Gang Qiu et al. |
|---|---|
| Primary category | cs.AI |
| Published | 5 October 2026 |
| Last updated at source | 5 October 2026 |
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