Back to the Future: Rethinking EDA Infrastructure for Agentic Systems in Chip Design Verification
The unprecedented computational scale of modern artificial intelligence depends on complex, multi-billion-transistor Systems-on-Chip, yet the workflows that verify these chips remain stubbornly manual. Although Large Language Models (LLMs) have made rapid inroads into Electronic Design Automation (EDA), approximately 74.6% of existing studies target static Register-Transfer Level (RTL) code generation, leaving post-simulation verification and interactive waveform debugging largely untouched. We introduce Back-to-the-Future (BTTF), an end-to-end agentic framework that closes this infrastructural gap. BTTF distills massive, unstructured simulation dumps into a normalized relational SQLite d...
| Authors | Je Yang, Ivan Lobov, Thomas Karpati |
|---|---|
| Primary category | cs.AI |
| Published | 5 October 2026 |
| Last updated at source | 5 October 2026 |
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