MeshKV: A Network-on-Chip KV Cache Fabric for Scalable Transformer Decoding Accelerators
Autoregressive transformer decoding is constrained by irregular key-value (KV) cache movement on tiled accelerators. Prior compression and DRAM-placement systems still concentrate traffic on centralized memory paths that bottleneck long-context serving. We present MeshKV, a KV cache fabric that moves blocks as packetized flows over a lightweight NoC. It co-designs (i) TaKV affine striping to spread homes and cut hotspot load, (ii) Mare multicast with verified duplicate suppression, and (iii) Pad, which overlaps prefetch, tile multiply, and streaming softmax behind credit-aligned FIFOs. Together they convert bisection back-pressure into useful KV transfer. On our 8x8 FPGA implementation wi...
| Authors | Dong Liu, Yanxuan Yu |
|---|---|
| Primary category | cs.AR |
| Published | 16 September 2026 |
| Last updated at source | 16 September 2026 |
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