Para-Pipe: Exploiting Hierarchical Operator Parallelism of ML Computational Graphs on SoCs
As edge-based deep learning applications become more complex, optimizing performance on heterogeneous System-on-Chips (SoCs) presents unique challenges. Traditional pipelining techniques distributing the computation across different on-chip processing units, while effective for throughput, do not address the latency demands posed by modern neural networks with complex interdependencies and extensive operator parallelism. There is a potential in leveraging operator parallelism to enable concurrent execution across multiple processing units, thereby reducing inference latency. However, prioritizing pipelining or parallel execution often necessitates a compromise, where optimizing one perfor...
| Authors | Yujie Zhang, Huiying Lan, Ehsan Aghapour et al. |
|---|---|
| Primary category | cs.DC |
| Published | 3 September 2026 |
| Last updated at source | 3 September 2026 |
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