Tensor Seeks Layout: Formalizing Layout Selection for ML Compilers
Modern machine learning compilers select tensor memory layouts to minimize execution cost under hardware constraints. Layout selection is global: an operator may be fastest under one layout while its consumers prefer another, and aligning these preferences requires explicit layout conversions that can hurt model performance. Despite its practical importance, layout selection lacks a formal basis, so current compilers rely on ad-hoc heuristics. This paper presents the first formal study of layout selection in machine learning compilers. We formulate the problem as combinatorial optimization over dataflow graphs, minimizing the sum of operator execution costs and the per-tensor cost of thes...
| Authors | Clemens Eisenhofer, Yuwen Jia, Daniel Kroening et al. |
|---|---|
| Primary category | cs.PL |
| Published | 21 August 2026 |
| Last updated at source | 21 August 2026 |
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