NetlistBench: Evaluating LLM Reliability in SPICE Netlist Recognition and Manipulation
Large Language Models (LLMs) are increasingly used in circuit design workflows, yet their reliability on simulator-facing SPICE netlist recognition and manipulation remains poorly understood and is rarely separated from high-level design reasoning. Although netlists are textual, they encode structured circuit objects through topology and parameters. We present \textbf{NetlistBench}, a structure-verified benchmark for SPICE netlist recognition and manipulation. NetlistBench contains 2,342 cases across 24 task families, covering parameter and connectivity recognition and edits, hierarchical operations, equivalence judgment, and long-horizon compound editing. Model outputs are evaluated by a...
| Authors | Jiarui Ma, Jianghan Wang, Yuheng Ma et al. |
|---|---|
| Primary category | eess.SY |
| Published | 12 August 2026 |
| Last updated at source | 12 August 2026 |
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