Self-Organising Digital Circuits
Fault tolerance in classical computing has traditionally relied on static strategies like hardware redundancy and error-correcting codes. Biological systems, in contrast, exhibit adaptive plasticity, maintaining function through dynamic re-organisation around damage. Inspired by this principle, we introduce Self-Organising Digital Circuits, framing functional logic generation and maintenance as a meta-learning problem on graphs. Our architecture employs a topology-masked Transformer that configures the Lookup Tables (LUT) of a circuit's Boolean gates. Extending the pattern-generation paradigm of Neural Cellular Automata (NCA), it navigates the degenerate Boolean search space to satisfy a ...
| Authors | Marcello Barylli, Gabriel Béna, Alexander Mordvintsev et al. |
|---|---|
| Primary category | cs.AI |
| Published | 7 May 2026 |
| Last updated at source | 14 August 2026 |
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