On the Limits of Machine-Learned Ranking for Modern Microarchitectural Policies
Machine-learning predictors estimate processor performance far faster than cycle-level simulation. For design-space exploration, however, the valuable test is not merely reproducing the usual hardware ordering, but identifying how different hardware configurations rank on individual program phases. We evaluate four ML-predictors in two design regimes: \emph{Structural Parameters} (SP), varying hardware resources such as issue width, ROB size, and cache capacity; and \emph{Behavioral Policies} (BP), varying prefetching and replacement algorithms. In the SP regime, aggregate ranking is strong, yet counter-intuitive windows(CIW)---where the configuration expected to be slower is faster---con...
| Authors | Yanxin Zhang, Shayne Wadle, Yuxuan Xiong et al. |
|---|---|
| Primary category | cs.AR |
| Published | 2 August 2026 |
| Last updated at source | 18 September 2026 |
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