FinHardBench: Can LLMs Generate Latency-Aware Hardware for Financial Computing?
Can large language models generate not just correct, but fast hardware? This paper investigates the question in financial FPGA design, where 5-10 nanoseconds of latency determines competitive advantage and designs iterate continuously as protocols, strategies, and regulations evolve. FinHardBench, a benchmark of 33 financial computing tasks, is presented together with three experiments that mirror the real-world FPGA iteration cycle: generating new modules from specifications, tuning system-level configurations across a 6-stage trading pipeline, and adapting existing modules to specification changes. Evaluation of six LLMs on 1530+ experiment rounds yields three findings: (1) models achie...
| Authors | Weimin Fu, Hejia Zhang, Minghao Shao et al. |
|---|---|
| Primary category | cs.CL |
| Published | 2 August 2026 |
| Last updated at source | 2 August 2026 |
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