CascadeLUT: Information-Ordered Streaming Inference for Bandwidth-Constrained FPGAs
Mapping neural networks to FPGAs enables low-latency, energy-efficient inference, particularly for lookup table (LUT)-based models that eliminate multipliers and map directly to reconfigurable fabric. While prior work achieves high compute efficiency, it typically assumes full-sample availability, causing pipeline stalls in bandwidth-limited streaming scenarios. Here, the bottleneck shifts from computation to data movement, as large input transfers limit throughput and energy efficiency. We present CascadeLUT, an information-structured inference framework organized around bandwidth constraints. Instead of buffering the full input, features are partitioned into ordered subsets and predicti...
| Authors | Oliver Cassidy, Marta Andronic, George A. Constantinides |
|---|---|
| Primary category | cs.AR |
| Published | 1 August 2026 |
| Last updated at source | 1 August 2026 |
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