Investigating reservoir computing for branch prediction in pipelined processors using emerging CMOS memristor devices
This project aimed to develop a novel reservoir compute (RC) implementation framework targeting high-speed operation and integration with CMOS digital logic. With the target workload of branch prediction (BP) for multistage pipelined central pro-cessing unit (CPU) cores. For this, a novel memristor based RC design framework was developed within the context of the workload requirements. This was then implemented in simulation using industry standard modelling languages of System Verilog (SV) and Verilog-AMS (VAMS).The developed RC design framework was subsequently verified using a basic sequence detection task before further benchmarking for its effectiveness at BP. The developed RC framew...
| Authors | Harvey Samuel George Johnson, Sendy Phang |
|---|---|
| Primary category | cs.AR |
| Published | 29 July 2026 |
| Last updated at source | 4 August 2026 |
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