ParasGB: A Graph Benchmark Suite for Parasitic Estimation on AMS Circuits
As chip manufacturing processes advance to deep submicron nodes, parasitic interconnect effects increasingly dominate the performance of analog and mixed-signal (AMS) circuits and often lead to costly layout iterations. This makes early-stage estimation of parasitic capacitance and resistance important for parasitic-aware design exploration before full physical implementation. However, progress on GNN-based parasitic modeling has been hindered by the lack of public, high-fidelity RC benchmarks that support reproducible evaluation. To address this gap, we introduce ParasGB, the first open-source benchmark suite for pre-layout parasitic parameter prediction on circuit graphs. ParasGB provid...
| Authors | Jiajun Zou, Jiawei Liu, Ao Liu et al. |
|---|---|
| Primary category | cs.LG |
| Published | 25 July 2026 |
| Last updated at source | 25 July 2026 |
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