BRIM: Workload-Balanced Dual-Sided Bit-Serial Sparse Inference Accelerator
Bit-serial accelerators exploit bit-level sparsity to reduce DNN inference cost, but existing designs exploit sparsity on only one operand, bounding the speedup. Extending sparsity exploitation to both operands simultaneously yields compounding reductions in partial products but introduces a critical new bottleneck: workload imbalance. Because each concurrent weight - activation pair's execution cost depends on the product of two independently varying operand non-zero bit counts, pairs that must complete together finish at vastly different times, leaving faster computations idle. We show this limits PE utilization to 56 - 64% in existing dual-sided designs. We present BRIM, a hardware - s...
| Authors | Varun Manjunath, Ruokai Yin, Donghyun Lee et al. |
|---|---|
| Primary category | cs.AR |
| Published | 20 July 2026 |
| Last updated at source | 20 July 2026 |
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