ESBMC-PLC+: A Unified IEC 61131-3 Formal Verification Framework as a PLCverif Successor
PLCverif is the most mature open-source platform for PLC formal verification, developed at CERN and in production use since 2019. Yet it has two fundamental limitations: no support for Ladder Diagram (LD) programs, the dominant PLC notation, and reliance on CBMC as its primary backend, which restricts verification to bounded proofs. The PLCverif authors themselves identified ESBMC as the appropriate backend improvement. Prior work established ESBMC-PLC (a textual LD frontend with k-induction) and ESBMC-GraphPLC (graphical PLCopen XML support); together, they cover LD with unbounded proofs but not Structured Text (ST), and graphical LD with timer/counter function blocks remains unverifiabl...
| Authors | Pierre Dantas, Lucas Cordeiro, Waldir Junior |
|---|---|
| Primary category | cs.PL |
| Published | 22 June 2026 |
| Last updated at source | 24 June 2026 |
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