How LLMs Fail and Generalize in RTL Coding for Hardware Design?
Translating sequential programming priors into the parallel temporal logic of hardware design remains a crucial bottleneck for large language models(LLM). To investigate this, we introduce a new error taxonomy grounded in problem solvability, inspired by cognitive theory. Our taxonomy categorizes failures into syntactic, semantic, solvable functional, and unsolvable functional types. Evaluations reveal a strict empirical ceiling on the VerilogEval benchmark, as frontier models plateau at a 90.8% initial pass rate. These plateaus are defined by unsolvable functional errors, exposing persistent knowledge gaps immune to test time compute scaling. Furthermore, we expose a striking surface con...
| Authors | Guan-Ting Liu, Chao-Han Huck Yang, Chenhui Deng et al. |
|---|---|
| Primary category | cs.CL |
| Published | 26 April 2026 |
| Last updated at source | 26 April 2026 |
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