ReRAM-aware Model Finetuning addressing I-V Non-linearity and Retention Errors
Traditional CPU, GPU, and NPU architectures are increasingly limited by the von Neumann bottleneck. While In-Memory Computing (IMC) using ReRAM crossbar arrays offers a high-density, energy-efficient alternative, its practical deployment is constrained through their non-idealities. Existing hardware-aware training frameworks often require training from scratch, which is computationally prohibitive for modern large-scale models. In this work, we propose a finetuning-based hardware-aware training algorithm that enables robust DNN deployment on ReRAM with minimal training overhead. Our approach mitigates I-V non-linearity by applying a range-shrunk sinh transformation and incorporates retent...
| Authors | Ching-Yi Lin, Shamik Kundu, Arnab Raha et al. |
|---|---|
| Primary category | cs.LG |
| Published | 16 June 2026 |
| Last updated at source | 22 July 2026 |
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