Towards Autonomous Accelerator Design: FPGA Accelerator Generation with SECDA
Designing FPGA-based accelerators for modern artificial intelligence workloads requires exploring a large and complex hardware design space that involves architectural parameters, data flow strategies, and memory hierarchies, making the process very time consuming. While existing methodologies such as SECDA enable rapid hardware-software co-design through SystemC simulation and FPGA execution, identifying efficient accelerator configurations remains a largely manual process requiring extensive domain knowledge. SECDA-DSE is a framework that integrates Large Language Models (LLMs) into the SECDA ecosystem to guide design space exploration (DSE) of FPGA-based accelerators. It combines a str...
| Authors | Vinamra Sharma, Xingjian Fu, Jude Haris et al. |
|---|---|
| Primary category | cs.AR |
| Published | 9 June 2026 |
| Last updated at source | 9 June 2026 |
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