AssertLLM2: A Comprehensive LLM Benchmark for Assertion Generation from Design Specifications
Assertion-based verification (ABV) is a cornerstone of modern hardware design, yet manually translating design intent into formal SystemVerilog Assertions (SVAs) remains labor-intensive and error-prone. While Large Language Models (LLMs) show promise for automating this process, existing benchmarks remain limited by unrealistic task formulations, weak specification inputs, and oversimplified evaluation. To address these limitations, we introduce AssertLLM2, an open-source benchmark for realistic assertion generation in hardware verification. AssertLLM2 contains 83 real-world designs across 13 functional categories. For each design, the benchmark provides a structured design specification,...
| Authors | Yuchao Wu, Wenji Fang, Jing Wang et al. |
|---|---|
| Primary category | cs.AR |
| Published | 26 May 2026 |
| Last updated at source | 26 May 2026 |
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