Heuristic-Based Merging of HPC Traces to Extend Hardware Counter Coverage
This work extends a framework for predicting the performance of High-Performance Computing (HPC) workloads using Machine Learning (ML). A common limitation in performance modeling is the restricted number of hardware counters that can be collected simultaneously. To address this, we propose a heuristic-based methodology to merge execution traces from multiple runs, each instrumented with a different set of hardware counters. Our approach matches computation bursts across executions by analyzing MPI structure, timing, and communication patterns. This process enables the construction of a unified dataset that includes a wider set of hardware features without relying on multiplexing. The out...
| Authors | Júlia Orteu Aubach, Fabio Banchelli, Marc Clascà Ramírez et al. |
|---|---|
| Primary category | cs.PF |
| Published | 15 May 2026 |
| Last updated at source | 15 May 2026 |
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