Autoformalizing Memory Specifications with Agents
The primary goal of Design Verification (DV) is to ensure that a proposed chip design implementation (either in code, or physical form) exactly matches its specification and is free of functional errors in order to avoid costly re-designs. Achieving this often demands extensive manual interpretation, translating the specification document into a formal, testable representation. While AI has made progress in DV, current approaches typically focus on narrow, isolated tasks rather than full end-to-end specification compliance of modern chip designs, failing to capture the complexity of real-world verification. Our method automatically formalizes natural language memory chip specifications, f...
| Authors | Jan Ole Ernst, Dmitri Michelangelo Saberi, Derek Christ et al. |
|---|---|
| Primary category | cs.AR |
| Published | 30 April 2026 |
| Last updated at source | 30 April 2026 |
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