Arch: An AI-Native Hardware Description Language for Register-Transfer Clocked Hardware Design

We present Arch (AI-native Register-transfer Clocked Hardware), a hardware description language for micro-architecture specification and AI-assisted code generation. Arch provides first-class constructs for pipelines, FSMs, FIFOs, arbiters, register files, buses with handshake channels, clock-domain crossings, and multi-cycle threads -- structures that existing HDLs express only as user-defined patterns prone to subtle errors. A central design choice is that clocks and resets are parameterized types (Clock<D>, Reset<S,P,D?>) rather than ordinary nets, converting CDC and reset-domain analysis from external linter passes into compile-time typing rules. Bit widths, port directions, single-dr...

<iframe src="https://silytics.si/embed/item/f69b7295-1618-4c17-a17f-3eb23d330160" width="420" height="190" style="border:0" loading="lazy" title="Silytics entry"></iframe>

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