VeriHGN: Heterogeneous Graph-Based Congestion Prediction for Chip Layout Verification
As Very Large Scale Integration (VLSI) designs continue to scale in size and complexity, layout verification has become a central challenge in modern Electronic Design Automation (EDA) workflows. In practice, congestion can only be accurately identified after detailed routing, making traditional verification both time-consuming and costly. Learning-based approaches have therefore been explored to enable early-stage congestion prediction and reduce routing iterations. However, although prior methods incorporate both netlist connectivity and layout features, they often model the two in a loosely coupled manner and primarily produce numerical congestion estimates. We propose VeriHGN, a verif...
| Authors | Runbang Hu, Bo Fang, Bingzhe Li et al. |
|---|---|
| Primary category | cs.AR |
| Published | 10 March 2026 |
| Last updated at source | 4 June 2026 |
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