When Small Variations Become Big Failures: Reliability Challenges in Compute-in-Memory Neural Accelerators
Compute-in-memory (CiM) architectures promise significant improvements in energy efficiency and throughput for deep neural network acceleration by alleviating the von Neumann bottleneck. However, their reliance on emerging non-volatile memory devices introduces device-level non-idealities-such as write variability, conductance drift, and stochastic noise-that fundamentally challenge reliability, predictability, and safety, especially in safety-critical applications. This talk examines the reliability limits of CiM-based neural accelerators and presents a series of techniques that bridge device physics, architecture, and learning algorithms to address these challenges. We first demonstrate...
| Authors | Yifan Qin, Jiahao Zheng, Zheyu Yan et al. |
|---|---|
| Primary category | cs.LG |
| Published | 3 March 2026 |
| Last updated at source | 3 March 2026 |
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