Multi-Head Low-Rank Attention
Long-context inference in large language models is bottlenecked by Key--Value (KV) cache loading during the decoding stage, where the sequential nature of generation requires repeatedly transferring the KV cache from off-chip High-Bandwidth Memory (HBM) to on-chip Static Random-Access Memory (SRAM) at each step. While Multi-Head Latent Attention (MLA) significantly reduces the total KV cache size, it suffers from a sharding bottleneck during distributed decoding via Tensor Parallelism (TP). Since its single latent head cannot be partitioned, each device is forced to redundantly load the complete KV cache for every token, consuming excessive memory traffic and diminishing TP benefits like ...
| Authors | Songtao Liu, Hongwu Peng, Zhiwei Zhang et al. |
|---|---|
| Primary category | cs.LG |
| Published | 2 March 2026 |
| Last updated at source | 2 March 2026 |
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