synthseq/flipflop

Data for Flip-Flop Language Modeling. The task is to correctly execute the sequential operations of a 1-bit register. The Transformer architecture, despite being apparently built for this operation, makes sporadic extrapolation errors (attention glitches). An open challenge is to fix these without recourse to long-tailed data or a recurrent architecture. Splits reflect the FFLM setup from the paper: train: 1.6M sequences from FFL(0.8) (256 instructions, 80% ignore, 10% read, 10% write). val:… See the full description on the dataset page: https://huggingface.co/datasets/synthseq/flipflop.

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