mktnhr/BitState

BitState / HSDR PoC Technical Brief — v0.5 Status: experimental engineering proposal, not a performance claim.Primary target: low-bit / ternary LLM GEMV, batch-1 decode first.Suggested first integration target: PrismML llama.cpp fork / Bonsai 2, CPU first. 1. Core hypothesis: move reduction into the state domain BitState/HSDR v0.5 centers the PoC on one implementation question: Move the reduction into the state domain to break the serial arithmetic reduction… See the full description on the dataset page: https://huggingface.co/datasets/mktnhr/BitState.

<iframe src="https://silytics.si/embed/item/4d9aa0d2-2f8c-47c3-b40b-f43167df685c" width="420" height="190" style="border:0" loading="lazy" title="Silytics entry"></iframe>

Silytics shows public metadata from Hugging Face and links to the original. Information may be incomplete or out of date. Last refreshed 18 October 2026. Licenses and terms of the original apply to the work itself. Not financial, legal or professional advice.