mcc311/haven-hdl-benchmark
HAVEN HDL Benchmark Suite 16 open-source IP designs for evaluating automated UVM testbench generation. Structure Each design contains: rtl/ — Verilog RTL source files spec/ — Specification documents (spec.md, impl_spec.md, vspec.md) haven.json — Per-design configuration (optional) Designs (16) # Design Protocol RTL Modules Source 1 aes Direct 5 Custom 2 alu Direct 1 Custom 3 sha3 Direct 6 OpenCores 4 spi Wishbone 2 OpenCores 5… See the full description on the dataset page: https://huggingface.co/datasets/mcc311/haven-hdl-benchmark.
| Author / organization | mcc311 |
|---|---|
| License (as declared) | mit |
| Downloads | 422 (as reported by Hugging Face) |
| Likes | 0 |
| Created | 16 March 2026 |
| Last updated at source | 16 March 2026 |
Popularity, last 3 days
422 now (-43 since 2026-10-16). Counts as reported by the source, snapshotted daily by Silytics.
Recent changes
- 17 Oct 2026 Description: HAVEN HDL Benchmark Suite 16 open-source IP designs for evaluating automated UVM testbench generation. Structure Each design contains: rtl/ — Verilog RTL source files spec/ — Specification documents (spec.md, impl_spec.md, vspec.md) haven.j → HAVEN HDL Benchmark Suite 16 open-source IP designs for evaluating automated UVM testbench generation. Structure Each design contains: rtl/ — Verilog RTL source files spec/ — Specification documents (spec.md, impl_spec.md, vspec.md) haven.j
Changes detected by Silytics between refreshes of the source.
Silytics shows public metadata from Hugging Face and links to the original. Information may be incomplete or out of date. Last refreshed 18 October 2026. Licenses and terms of the original apply to the work itself. Not financial, legal or professional advice.