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aditigupta/EquivSVA

EquivSVA EquivSVA is a formally verified dataset of behavioral SystemVerilog Assertions across equivalent RTL implementations. See the paper and the full GitHub repository for generators, validation scripts, and experiment artifacts. Contents The dataset has 120 behavior families across 12 categories. Every family contains four equivalent reference RTL implementations, shared gold properties, and three controlled mutants. The complete dataset has 480 reference RTL… See the full description on the dataset page: https://huggingface.co/datasets/aditigupta/EquivSVA.

Author / organizationaditigupta
License (as declared)cc-by-4.0
Downloads135 (as reported by Hugging Face)
Likes0
Created23 September 2026
Last updated at source23 September 2026
systemverilogformal-verificationhardware-verificationassertion-generation
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