adimnaku/fpga_cost_model_kernel_data
FPGA HLS Kernel Cost-Model Data Evolved Vitis HLS C++ kernels paired with their ground-truth Vitis HLS csynth results. Each row is one generated program from an evolutionary FPGA optimisation run, linked to its kernel source, evaluator report.json, and raw synthesis report. Each row carries a split label: train marks the original benchmarks used to fit the analytical cost model's learned correction term, and holdout marks benchmarks added afterwards that were not used for… See the full description on the dataset page: https://huggingface.co/datasets/adimnaku/fpga_cost_model_kernel_data.
| Author / organization | adimnaku |
|---|---|
| License (as declared) | mit |
| Downloads | 500 (as reported by Hugging Face) |
| Likes | 0 |
| Created | 14 July 2026 |
| Last updated at source | 15 July 2026 |
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