HPAI-BSC/SystemVerilog-SFT-86k

SystemVerilog SFT 85,701 validated examples for supervised fine-tuning on design verification: test-plan generation from RTL and self-checking SystemVerilog testbench generation conditioned on RTL and a test plan. The dataset distills Gemma-4-31B teacher responses, including reasoning, generated at scale using vLLM with 8 data-parallel replicas across 32 H100 GPUs. All released examples come from validated (DUT, test-plan, testbench) triplets: the generated testbench must… See the full description on the dataset page: https://huggingface.co/datasets/HPAI-BSC/SystemVerilog-SFT-86k.

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