HPAI-BSC/SystemVerilog-RL-12k

SystemVerilog RL An RL dataset for SystemVerilog verification tasks. For each row, we ask the model to produce a self-checking testbench; a good testbench must pass on the golden design and fail on the mutants. The dataset contains 11,902 problems, with up to 20 Yosys-generated netlist mutations per problem. Feel free to use whatever EDA tooling, although this environment was used with both Icarus Verilog and Verilator. 🤗 Models Qwen3.6-27B-RL-Verif Qwen3.5-9B-RL-Verif 🤗… See the full description on the dataset page: https://huggingface.co/datasets/HPAI-BSC/SystemVerilog-RL-12k.

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